1. Field of the Invention
The present invention relates to a method of fabricating semiconductor memory device. More particularly, the present invention relates to a method of fabricating non-volatile memory.
2. Description of the Related Art
Among the various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used inside personal computer systems and electronic equipment. In the EEPROM, data can be stored, read out or erased numerous times and stored data are retained even after power is cut off.
Typically, the floating gate and the control gate of an EEPROM cell are fabricated using doped polysilicon. In the conventional technique, a charge-trapping layer is sometimes used to replace a floating gate fabricated from polysilicon material. The charge-trapping layer is, for example, fabricated using silicon nitride. In general, an oxide layer is formed both above and below the silicon nitride charge-trapping layer to form an oxide-nitride-oxide (ONO) composite structure. This type of memory is often referred to as a silicon-oxide-nitride-oxide-silicon (SONOS) memory device.
The semiconductor manufacturers have produce one kind of non-volatile memory with a structure shown schematically in FIG. 1. The non-volatile memory includes a memory cell column having a plurality of first memory cells 102 and a plurality of second memory cells 116. The first memory cells 102 are separated from the second memory cells 116 through insulating spacers 110 respectively. Each first memory cell 102 includes a bottom dielectric layer 104a, a charge-trapping layer 104b, a top dielectric layer 104c (the bottom dielectric layer 104a, the charge-trapping layer 104b and the top dielectric layer 104c together form a composite layer 104), a gate 106 and a cap layer 108 sequentially stacked on the substrate 100. Each second memory cell 116 similarly includes a bottom dielectric layer 112a, a charge-trapping layer 112b, a top dielectric layer 112c (the bottom dielectric layer 112a, the charge-trapping layer 112b and the top dielectric layer 112c together form a composite layer 112) and a gate 114 sequentially stacked on the substrate 100. Because there is no gap between neighboring memory cells, the level of integration of devices for this type of non-volatile memory is increased.
However, the gates 106 of the first memory cells 102 are fabricated from a polycide material that includes a doped polysilicon layer 106a and a metal silicide layer 106b. On the other hand, the gates 114 of the second memory cells 116 are fabricated from a doped polysilicon material. Since the doped polysilicon material has a resistance much greater than the polycide material, there is a significant difference in the electrical performance between the first memory cells 102 and the second memory cells 116. Hence, there will be a drop in the electrical performance of the devices and a greater instability in the device process.